P1.20 TRACESYNC Trace Synchronization. Standard I/O port with internal pull-up. LOW on this pin while RESET is LOW enables pins P1.25:16 to operate as a Trace port after reset.
Important: LOW on pin P1.20 while RESET is LOW enables pins P1.25:16 to operate as a Trace port after reset.
P1.26 RTCK Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bi-directional pin with internal pullup. LOW on this pin while RESET is LOW enables pins P1.31:26 to operate as a Debug port after reset.
Important: LOW on pin P1.26 while RESET is LOW enables pins P1.31:26 to operate as a Debug port after reset.
P2.26 D26 External memory data line 26.
BOOT0 While RESET is low, together with BOOT1 controls booting and internal operation. Internal pullup ensures high state if pin is left unconnected.
P2.27 D27 External memory data line 27.
BOOT1 While RESET is low, together with BOOT0 controls booting and internal operation.Internal pullup ensures high state if pin is left unconnected.
BOOT1:0=00 selects 8-bit memory on CS0 for boot.
BOOT1:0=01 selects 16-bit memory on CS0 for boot.
BOOT1:0=10 selects 32-bit memory on CS0 for boot.
BOOT1:0=11 selects Internal Flash memory.
P0.14 DCD1 Data Carrier Detect input for UART1.
EINT1 External interrupt 1 input. LOW on this pin while RESET is LOW forces on-chip boot-loader to take over control of the part after reset.
Important: LOW on pin P0.14 while RESET is LOW forces on-chip bootloader to take over control of the part after reset.
根据LPC2294启动流程，若是硬复位（上电复位、手动复位）上述引脚都将得到检测；软复位（如看门狗复位）将会跳过P0.14引脚的检测，而其他引脚仍会得到检测。
