1、CAN错误检测(Error Detection)
CAN网络具有严格的错误诊断功能,该功能已固化在硅片之中,一旦错误被检测,正在传送的数据帧将会立即停止而待总线空闲时再次重发直至发送成功,该过程并不需要CPU的干涉除非错误累计该发送器退隐(Bus Off)。CAN控制器可检测如下五种错误:
√ 位错误(Bit Check Error)
发送器在发送比特流的同时也对发出的比特流采样回收,若送出的bit与所期待的bit不合,则会检测到一个Bit Check Error;
√ 位填充错误(Bit Stuff Error)
在需要执行位编码规则的位流序列中检测到第6个连续的极性相同的位序流时,则检测到一个Bit Stuff Error;
√ CRC 错误(CRC Error)
发送端送出的CRC序列由发送器算出,接收器执行同样的CRC算法,若计算结果与接收到的CRC序列不符,一个CRC Error被检测到,由发送端送出;
√ 帧格式错误(Frame Check Error)
当一个固定形式的位场含非法位,则检测到一个Frame Check Error(接收端检测到帧结束最后一位为显性时帧错误忽略);
√ 应答错误(Acknowledgment Error)
ACK SLOT采样为隐性,则检测到一个Acknowledgement Error;
2、CAN错误界定(Error Confinement)
CAN控制器内置两个错误计数器:Receive Error Counter及Tranmit Error Counter(错误计数器的计数规则后附)。当某个计数器的当前值达到128时,CAN控制器将进入“Error Passive Mode”,此时该节点仍然参与CAN通讯,检测到错误时只能发送“Error Passive Flag”,且错误帧发送完毕重启下一个发送之前有8bits位时的挂起状态;当Tranmit Error Counter当前值为255接着又一个错误被检测到时,CAN控制器将进入“Bus Off Mode”,此时该节点与总线完全脱离,整个瘫痪;计数器当前值均小于128时,CAN控制器被标识为“Error Active Mode”,CAN节点可正常通讯并检测到错误时发送“Error Active Flag”。这三种状态之间关系为:

3、LPC2294中的CAN控制器错误处理
LPC2294内置的CAN控制模块完全符合CAN Spec 2.0B,当CAN控制器被迫进入BusOff状态后:CANGSR寄存器中的BS位置位;CANICR中的BEI位置位,若CANIER寄存器的BEIE使能,将引发CAN中断;CANMOD中的RM置位,CAN控制器处于复位状态;同时发送错误计数器被设置为127,接收错误计数器清零。CAN控制器进入BusOff状态后必须由软件复位RM位,以恢复通讯;RM清零进入Normal Operation状态后,当检测到总线上11bits的连续隐性位流出现128次之后,发送错误计数器清零,CANGSR中的BS、ES位清零,同时若中断允许,将产生中断,CAN控制器重返CAN通讯。
4、CAN2.0B(Active)规范的错误计数器的计数规则:
1. When a RECEIVER detects an error, the RECEIVE ERROR COUNT will be increased by 1, except when the detected error was a BIT ERROR during the sending of an ACTIVE ERROR FLAG or an OVERLOAD FLAG.
2. When a RECEIVER detects a ’dominant’ bit as the first bit after sending an ERROR FLAG the RECEIVE ERROR COUNT will be increased by 8.
3. When a TRANSMITTER sends an ERROR FLAG the TRANSMIT ERROR COUNT is
increased by 8.
Exception 1:
If the TRANSMITTER is ’error passive’ and detects an ACKNOWLEDGEMENT ERROR because of not detecting a ’dominant’ ACK and does not detect a ’dominant’ bit while sending its PASSIVE ERROR FLAG.
Exception 2:
If the TRANSMITTER sends an ERROR FLAG because a STUFF ERROR occurred during ARBITRATION, and should have been ’recessive’, and has been sent as ’recessive’ but monitored as ’dominant’.
In exceptions 1 and 2 the TRANSMIT ERROR COUNT is not changed.
4. If an TRANSMITTER detects a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG the TRANSMIT ERROR COUNT is increased by 8.
5. If an RECEIVER detects a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG the RECEIVE ERROR COUNT is increased by 8.
6. Any node tolerates up to 7 consecutive ’dominant’ bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or OVERLOAD FLAG. After detecting the 14th consecutive ’dominant’ bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD FLAG) or after detecting the 8th consecutive ’dominant’ bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive ’dominant’ bits every TRANSMITTER increases its TRANSMIT ERROR COUNT by 8 and every RECEIVER increases its RECEIVE ERROR COUNT by 8.
7. After the successful transmission of a message (getting ACK and no error until END OF FRAME is finished) the TRANSMIT ERROR COUNT is decreased by 1 unless it was already 0.
8. After the successful reception of a message (reception without error up to the ACK SLOT and the successful sending of the ACK bit), the RECEIVE ERROR COUNT is decreased by 1, if it was between 1 and 127. If the RECEIVE ERROR COUNT was 0, it stays 0, and if it was greater than 127, then it will be set to a value between 119 and 127.
9. A node is ’error passive’ when the TRANSMIT ERROR COUNT equals or exceeds 128, or when the RECEIVE ERROR COUNT equals or exceeds 128. An error condition letting a node become ’error passive’ causes the node to send an ACTIVE ERROR FLAG.
10. A node is ’bus off’ when the TRANSMIT ERROR COUNT is greater than or equal to 256.
11. An ’error passive’ node becomes ’error active’ again when both the TRANSMIT ERROR COUNT and the RECEIVE ERROR COUNT are less than or equal to 127.
12. An node which is ’bus off’ is permitted to become ’error active’ (no longer ’bus off’) with its error counters both set to 0 after 128 occurrances of 11 consecutive ’recessive’ bits have been monitored on the bus.
Note:
An error count value greater than about 96 indicates a heavily disturbed bus. It may be of advantage to provide means to test for this condition.
5、未完待续...